About ghdl
GHDL is a tool for analyzing, compiling, and simulating VHDL, with experimental synthesis also identified as a capability. VHDL is a hardware description language used to express digital logic designs. Analysis checks a design’s source, compilation translates it into a form that can be used by a simulator, and simulation helps evaluate how the described logic behaves. Synthesis, when supported, translates a design toward a hardware implementation; the supplied information explicitly characterizes that capability as experimental. GHDL therefore supports several stages of working with VHDL designs, from checking source to testing behavior. The available product information does not specify language-standard coverage, supported target hardware, simulation features, or operating systems. Those technical details should be checked for a particular design workflow.
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