About yosys
Yosys is a framework for Verilog RTL synthesis. Verilog is a hardware description language, and RTL, or register-transfer level, describes digital circuits in terms of data movement and operations between registers. Synthesis transforms that description into a representation suitable for later hardware implementation steps. Yosys therefore serves electronic design and hardware development workflows rather than ordinary software compilation. The available product information does not specify supported Verilog features, target hardware, synthesis flows, or output formats. Those details should be verified for a particular design. Its documented purpose is to provide a framework for synthesizing Verilog RTL. The framework’s input language is Verilog RTL.
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